I. Field of the Invention
The present invention relates generally to a multi-layered complementary wire structure and a manufacturing method thereof, and more particularly, to a multi-layered complementary wire structure and a manufacturing method thereof that can substantially reduce the resistance of the wire.
II. Background Art
With rapid developments in multimedia techniques, advanced peripheral audio-visual equipments are increasingly demanded by users. A conventional display composed of a cathode ray tube (CRT) or an image tube can no longer satisfy the current demands for compact, lightweight equipments. Recently, many flat panel display technologies, such as the liquid crystal display (LCD), plasma display panel (PDP) display and field emission display (FED), have been developed sequentially and have become the standards in display technology.
FIG. 1 illustrates a schematic diagram of a thin film transistor array plate of a conventional display. Referring to FIG. 1, a thin film transistor array plate 10 comprises a plurality of pixel units, i.e. pixels 18, arranged in a matrix. Each of the pixels 18 includes a thin film transistor 16, and the pixels 18 are separated by a plurality of gate lines 14 formed laterally in parallel to each other and a plurality of data lines 12 formed vertically in parallel to each other. The gate lines 14 and the data lines 12 are connected to the thin film transistors 16 of the pixels 18.
FIG. 2 illustrates a schematic diagram of a pixel of a conventional display. Referring to FIG. 2, each pixel 18 includes a thin film transistor 16. Each gate line 14 is connected to a gate 26 of the thin film transistor 16, and each data line 12 is connected to a source 20 and a drain 22 of the thin film transistor 16. An insulating layer (not shown) and an active layer 24 are located between the gate 26, the source 20 and the drain 22. Moreover, each pixel 18 further comprises a pixel electrode 28, which is connected to the drain 22. The thin film transistor 16 functions to serve as a switch device for the pixel electrode 28.
In general, each gate line 14 and each data line 12 are located in different metal layers. In the overlapping regions of the gate lines 14 and the data lines 12, the gate lines 14 are not connected to the data lines 12 and are insulated by insulating layers 30 peripherally, such as shown in FIG. 3. As displays become larger in size, gate lines and data lines become longer. As a result, the overall resistance of the gate lines and data lines increase, which may disadvantageously incur undesired resistance-capacitance delay (RC delay) and adversely affect the operating speed of the display devices.